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TCA6424A 割り込み出力、リセット、構成レジスタ付き、低電圧 24 ビット I2C および SMBus I/O エクスパンダ
JAJSPM3D
July 2010 – January 2023
TCA6424A
PRODUCTION DATA
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TCA6424A 割り込み出力、リセット、構成レジスタ付き、低電圧 24 ビット I2C および SMBus I/O エクスパンダ
1
特長
2
概要
3
Revision History
4
Description (continued)
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings (1)
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
I2C Interface Timing Requirements
6.7
Reset Timing Requirements
6.8
Switching Characteristics
6.9
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.1.1
Voltage Translation
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
I/O Port
8.3.2
I2C Interface
8.4
Device Functional Modes
8.4.1
Device Address
8.5
Programming
8.5.1
Power-On Reset
8.5.2
Reset Input ( RESET)
8.5.3
Interrupt Output ( INT)
8.5.4
Bus Transactions
8.5.4.1
Writes
8.5.4.2
Reads
8.6
Register Maps
8.6.1
Control Register and Command Byte
8.6.2
Register Descriptions
9
Application and Implementation
9.1
Typical Application
9.1.1
Detailed Design Procedure
9.1.1.1
Minimizing ICC When I/Os Control LEDs
9.2
Power Supply Recommendation
10
Device and Documentation Support
10.1
Receiving Notification of Documentation Updates
10.2
サポート・リソース
10.3
商標
10.4
静電気放電に関する注意事項
10.5
用語集
Mechanical, Packaging, and Orderable Information
重要なお知らせ
パッケージ・オプション
メカニカル・データ（パッケージ｜ピン）
RGJ|32
MPQF183D
サーマルパッド・メカニカル・データ
発注情報
jajspm3d_oa
jajspm3d_pm
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