SNLS200B
September 2005 – January 2019
DS90LV049H
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Device Images
Dual-In-Line
Functional Diagram
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Switching Characteristics
6.7
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
DS90LV049H LVDS Driver and Receiver Functionality
8.3.2
Termination
8.3.3
Fail-Safe Feature
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Power Decoupling Recommendations
9.2.2.2
PCB Transmission Lines
9.2.2.3
Input Fail-Safe Biasing
9.2.2.4
Probing LVDS Transmission Lines on PCB
9.2.2.5
Interconnecting Media
9.2.3
Application Curve
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.1.1
Microstrip vs. Stripline Topologies
11.1.2
Dielectric Type and Board Construction
11.1.3
Recommended Stack Layout
11.1.4
Separation Between Traces
11.1.5
Crosstalk and Ground Bounce Minimization
11.1.6
Decoupling
11.2
Layout Example
12
Device and Documentation Support
12.1
Related Documentation
12.2
Receiving Notification of Documentation Updates
12.3
Community Resources
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
PW|16
MPDS361A
Thermal pad, mechanical data (Package|Pins)
Orderable Information
snls200b_oa
snls200b_pm
1
Features
High Temperature +125°C Operating Range
Up to 400-Mbps Switching Rates
Flow-Through Pinout Simplifies PCB Layout
50-ps Typical Driver Channel-to-Channel Skew
50-ps Typical Receiver Channel-to-Channel Skew
3.3-V Single Power Supply Design
TRI-STATE Output Control
Internal Fail-Safe Biasing of Receiver Inputs
Low Power Dissipation (70 mW at 3.3-V Static)
High Impedance on LVDS Outputs on Power Down
Conforms to TIA/EIA-644-A LVDS Standard
Available in Low Profile 16-Pin TSSOP Package