SNLS011D July   1999  – August 2016 DS90LV032A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Dissipation Ratings
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Fail-Safe Feature
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Probing LVDS Transmission Lines
      2. 9.1.2 Cables and Connectors, General Comments
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Probing LVDS Transmission Lines
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Power Decoupling Recommendations
      2. 11.1.2 Differential Traces
      3. 11.1.3 Termination
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • >400 Mbps (200 MHz) Switching Rates
  • 0.1-ns Channel-to-Channel Skew (Typical)
  • 0.1-ns Differential Skew (Typical)
  • 3.3-ns Maximum Propagation Delay
  • 3.3-V Power Supply Design
  • Power Down High Impedance on LVDS Inputs
  • Low Power Design (40 mW at 3.3 V Static)
  • Interoperable With Existing 5-V LVDS Networks
  • Accepts Small Swing (350 mV Typical) VID
  • Supports Open, Short, and Terminated Input Fail-Safe
  • Compatible With ANSI/TIA/EIA-644
  • Industrial Temperature Operating Range (–40°C to 85°C)
  • Available in SOIC and TSSOP Packaging

2 Applications

  • Building And Factory Automation
  • Grid Infrastructure

3 Description

The DS90LV032A is a quad CMOS differential line receiver designed for applications requiring ultra-low power dissipation and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) using Low Voltage Differential Signaling (LVDS) technology.

The DS90LV032A accepts low voltage (350 mV typical) differential input signals and translates them to 3-V CMOS output levels. The receiver supports a TRI-STATE function that may be used to multiplex outputs. The receiver also supports open, shorted, and terminated (100 Ω) input Fail-safe. The receiver output is HIGH for all fail-safe conditions.

The DS90LV032A and companion LVDS line driver (for example, DS90LV031A) provide a new alternative to high power PECL or ECL devices for high speed point-to-point interface applications.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
DS90LV032A SOIC (16) 9.90 mm × 3.91 mm
TSSOP (16) 5.00 mm × 4.40 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Block Diagram

DS90LV032A 10006702.gif