SNLS199B
September 2005 – January 2019
DS90LT012AH
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Device Images
Connection Diagram
Functional Diagram
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Switching Characteristics
6.7
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Termination
8.3.2
Threshold
8.3.3
Fail-Safe Feature
8.3.4
Probing LVDS Transmission Lines
8.3.5
Cables and Connectors, General Comments
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Point-to-Point Communications
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.2.1
Receiver Bypass Capacitance
9.2.1.2.2
Interconnecting Media
9.2.1.2.3
PCB Transmission Lines
9.2.1.3
Application Curve
10
Power Supply Recommendations
10.1
Power Supply Considerations
11
Layout
11.1
Layout Guidelines
11.1.1
Microstrip vs. Stripline Topologies
11.1.2
Dielectric Type and Board Construction
11.1.3
Recommended Stack Layout
11.1.4
Separation Between Traces
11.1.5
Crosstalk and Ground Bounce Minimization
11.1.6
Decoupling
11.2
Layout Example
12
Device and Documentation Support
12.1
Receiving Notification of Documentation Updates
12.2
Community Resources
12.3
Trademarks
12.4
Electrostatic Discharge Caution
12.5
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DBV|5
MPDS018T
Thermal pad, mechanical data (Package|Pins)
Orderable Information
snls199b_oa
snls199b_pm
1
Features
–40°C to +125°C Temperature Range Operation
Compatible With ANSI TIA/EIA-644-A Standard
>400-Mbps (200-MHz) Switching Rates
100-ps Differential Skew (Typical)
3.5-ns Maximum Propagation Delay
Integrated Line Termination Resistor (100 Ω Typical)
Single 3.3-V Power Supply Design (2.7-V to 3.6-V Range)
Power-Down High Impedance on LVDS Inputs
LVDS Inputs Accept LVDS/CML/LVPECL Signals
Pinout Simplifies PCB Layout
Low Power Dissipation (10 mW Typical at 3.3-V Static)
5-Pin SOT-23 Package