SNLS459A APRIL   2013  – October 2015 DS125RT410

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Data Path Operation
      2. 7.3.2 Signal Detect
      3. 7.3.3 CTLE
      4. 7.3.4 Clock and Data Recovery
      5. 7.3.5 Output Driver
      6. 7.3.6 Device Configuration
        1. 7.3.6.1 Rate and Subrate Setting
    4. 7.4 Device Functional Modes
      1. 7.4.1 SMBus Master Mode and SMBus Slave Mode
      2. 7.4.2 Address Lines <ADDR_[3:0]>
      3. 7.4.3 SDA and SDC
      4. 7.4.4 Standards-Based Modes
        1. 7.4.4.1 Ref_mode 3 Mode (Reference Clock Required)
        2. 7.4.4.2 False Lock Detector Setting
        3. 7.4.4.3 Reference Clock In
        4. 7.4.4.4 Reference Clock Out
        5. 7.4.4.5 Driver Output Voltage
        6. 7.4.4.6 Driver Output De-Emphasis
        7. 7.4.4.7 Driver Output Rise and Fall Time
        8. 7.4.4.8 INT
        9. 7.4.4.9 LOCK_3, LOCK_2, LOCK_1, and LOCK_0
    5. 7.5 Programming
      1. 7.5.1  SMBus Strap Observation
      2. 7.5.2  Device Revision and Device ID
      3. 7.5.3  Control/Shared Register Reset
      4. 7.5.4  Interrupt Channel Flag Bits
      5. 7.5.5  SMBus Master Mode Control Bits
      6. 7.5.6  Resetting Individual Channels of the Retimer
      7. 7.5.7  Interrupt Status
      8. 7.5.8  Overriding the CTLE Boost Setting
      9. 7.5.9  Overriding the VCO Search Values
      10. 7.5.10 Overriding the Output Multiplexer
      11. 7.5.11 Overriding the VCO Divider Selection
      12. 7.5.12 Using the PRBS Generator
      13. 7.5.13 Using the Internal Eye Opening Monitor
      14. 7.5.14 Enabling Slow Rise and Fall Time on the Output Driver
      15. 7.5.15 Inverting the Output Polarity
      16. 7.5.16 Overriding the Figure of Merit for Adaptation
      17. 7.5.17 Setting the Rate and Subrate for Lock Acquisition
      18. 7.5.18 Setting the Adaptation/Lock Mode
      19. 7.5.19 Initiating Adaptation
      20. 7.5.20 Setting the Reference Enable Mode
      21. 7.5.21 Overriding the CTLE Settings Used for CTLE Adaptation
      22. 7.5.22 Setting the Output Differential Voltage
      23. 7.5.23 Setting the Output De-Emphasis Setting
    6. 7.6 Register Maps
      1. 7.6.1 Register Information
      2. 7.6.2 Bit Fields in the Register Set
      3. 7.6.3 Writing to and Reading from the Control/Shared Registers
      4. 7.6.4 Channel Select Register
      5. 7.6.5 Reading to and Writing from the Channel Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Each Channel Independently Locks to Data Rates From 9.8 to 12.5 Gbps and Submultiples
  • Fast Lock Operation Based on Protocol-Select Mode
  • Low Latency (≈300 ps)
  • Adaptive Equalization up to 34-dB Boost at 5 GHz
  • Adjustable Transmit VOD: 600 to 1300 mVp-p
  • Adjustable Transmit De-emphasis to –15 dB
  • Typical Power Dissipation (EQ+CDR+DE):
    150 mW/Channel
  • Programmable Output Polarity Inversion
  • Input Signal Detection, CDR Lock Detection and Indicator
  • On-Chip Eye Monitor (EOM), PRBS Generator
  • Single 2.5-V ± 5% Power Supply
  • SMBus and EEPROM Configuration Modes
  • Operating Temperature Range of –40 to 85°C
  • WQFN 48-Pin 7-mm × 7-mm Package
  • Easy Pin Compatible Upgrade Between Repeater and Retimers
    • DS100RT410 (EQ+CDR+DE): 10.3125 Gbps
    • DS100DF410 (EQ+DFE+CDR+DE):
      10.3125 Gbps
    • DS110RT410 (EQ+CDR+DE): 8.5 to
      11.3 Gbps
    • DS110DF410 (EQ+DFE+CDR+DE): 8.5 to 11.3 Gbps
    • DS125RT410 (EQ+CDR+DE): 9.8 to
      12.5 Gbps
    • DS125DF410 (EQ+DFE+CDR+DE):
      9.8 to 12.5 Gbps
    • DS100BR410 (EQ+DE): Up to 10.3125 Gbps

2 Applications

  • Front Port SFF 8431 (SFP+) Optical and Direct Attach Copper
  • Backplane Reach Extension, Data Retimer
  • Ethernet: 10 GbE, 1 GbE
  • CPRI: Line Bit Rate Options 3–7
  • Interlaken: All Lane Bit Rates
  • InfiniBand
  • Other Propriety Data Rates up to 12.5 Gbps

3 Description

The DS125RT410 is a four-channel retimer with integrated signal conditioning. The device includes a fully adaptive continuous-time linear equalizer (CTLE), clock and data recovery (CDR), and a transmit de-emphasis (DE) driver to enable data transmission over long, lossy and crosstalk-impaired highspeed serial links to achieve BER < 1 × 10–15. For channels with a high amount of crosstalk, the DS125DF410 should be used because it has self calibrating 5-tap decision-feedback equalizer (DFE).

Each channel can independently lock to data rate from 9.8 to 12.5 Gbps, and associated subrates (divide by 2, 4, and 8) to support a variety of communication protocols. A 25-MHz crystal oscillator clock is used to speed up the CDR lock process. This clock is not used for training the PLL and does not need to be synchronous with the serial data.

The programmable settings can be applied using the SMBus (I2C) interface, or they can be loaded through an external EEPROM. An on-chip eye monitor and a PRBS generator allow real-time measurement of high-speed serial data for system bring-up or field tuning.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
DS125RT410 WQFN (48) 7.00 mm × 7.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Typical Application Diagram

DS125RT410 30161080A.gif

4 Revision History

Changes from * Revision (April 2013) to A Revision

  • Added ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
  • Changed Channel Register 33 to Reserved. Go