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ADS9110 18-Bit, 2-MSPS, 15-mW, SAR ADC With Enhanced Performance Features
SBAS629B
October 2015 – June 2017
ADS9110
PRODUCTION DATA.
CONTENTS
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ADS9110 18-Bit, 2-MSPS, 15-mW, SAR ADC With Enhanced Performance Features
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements: Conversion Cycle
6.7
Timing Requirements: Asynchronous Reset, NAP, and PD
6.8
Timing Requirements: SPI-Compatible Serial Interface
6.9
Timing Requirements: Source-Synchronous Serial Interface (External Clock)
6.10
Timing Requirements: Source-Synchronous Serial Interface (Internal Clock)
6.11
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Converter Module
7.3.1.1
Sample-and-Hold Circuit
7.3.1.2
External Reference Source
7.3.1.3
Internal Oscillator
7.3.1.4
ADC Transfer Function
7.3.2
Interface Module
7.4
Device Functional Modes
7.4.1
RST State
7.4.2
ACQ State
7.4.3
CNV State
7.5
Programming
7.5.1
Data Transfer Frame
7.5.2
Interleaving Conversion Cycles and Data Transfer Frames
7.5.3
Data Transfer Protocols
7.5.3.1
Protocols for Configuring the Device
7.5.3.2
Protocols for Reading From the Device
7.5.3.2.1
Legacy, SPI-Compatible (SYS-xy-S) Protocols
7.5.3.2.2
SPI-Compatible Protocols with Bus Width Options
7.5.3.2.3
Source-Synchronous (SRC) Protocols
7.5.3.2.3.1
Output Clock Source Options with SRC Protocols
7.5.3.2.3.2
Bus Width Options with SRC Protocols
7.5.3.2.3.3
Output Data Rate Options with SRC Protocols
7.5.4
Device Setup
7.5.4.1
Single Device: All multiSPI™ Options
7.5.4.2
Single Device: Minimum Pins for a Standard SPI Interface
7.5.4.3
Multiple Devices: Daisy-Chain Topology
7.5.4.4
Multiple Devices: Star Topology
7.6
Register Maps
7.6.1
Device Configuration and Register Maps
7.6.1.1
PD_CNTL Register (address = 010h)
7.6.1.2
SDI_CNTL Register (address = 014h)
7.6.1.3
SDO_CNTL Register (address = 018h)
7.6.1.4
DATA_CNTL Register (address = 01Ch)
8
Application and Implementation
8.1
Application Information
8.1.1
ADC Input Driver
8.1.2
Input Amplifier Selection
8.1.3
Charge Kickback Filter
8.1.4
ADC Reference Driver
8.2
Typical Application
8.2.1
Data Acquisition (DAQ) Circuit for Lowest Distortion and Noise Performance With Differential Input
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.3
Application Curves
8.2.2
DAQ Circuit With FDA Input Driver and Single-Ended or Differential Input
8.2.2.1
Design Requirements
8.2.2.2
Detailed Design Procedure
8.2.2.3
Application Curves
9
Power-Supply Recommendations
9.1
Power-Supply Decoupling
9.2
Power Saving
9.2.1
NAP Mode
9.2.2
PD Mode
10
Layout
10.1
Layout Guidelines
10.1.1
Signal Path
10.1.2
Grounding and PCB Stack-Up
10.1.3
Decoupling of Power Supplies
10.1.4
Reference Decoupling
10.1.5
Differential Input Decoupling
10.2
Layout Example
11
Device and Documentation Support
11.1
Documentation Support
11.1.1
Related Documentation
11.2
Receiving Notification of Documentation Updates
11.3
Community Resources
11.4
Trademarks
11.5
Electrostatic Discharge Caution
11.6
Glossary
12
Mechanical, Packaging, and Orderable Information
IMPORTANT NOTICE
Package Options
Mechanical Data (Package|Pins)
RGE|24
MPQF124G
Thermal pad, mechanical data (Package|Pins)
RGE|24
QFND136Y
Orderable Information
sbas629b_oa
sbas629b_pm
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