3 Description
The ADS85x8 contain eight low-power, 12-, 14-, or 16-bit, successive approximation register (SAR)-based analog-to-digital converters (ADCs) with true bipolar inputs. These channels are grouped in four pairs, thus allowing simultaneous high-speed signal acquisition of up to 650 kSPS.
The devices support selectable parallel or serial interface with daisy-chain capability. The programmable reference allows handling of analog input signals with amplitudes up to ±12 V.
The ADS85x8 family supports an auto-sleep mode for minimum power dissipation and is available in both 64-pin VQFN and LQFP packages. The entire family is specified over a temperature range of –40°C to +125°C.
Device Information(1)
PART NUMBER |
PACKAGE |
BODY SIZE (NOM) |
ADS85x8 |
VQFN (64) |
9.00 mm × 9.00 mm |
LQFP (64) |
10.00 mm × 10.00 mm |
- For all available packages, see the orderable addendum at the end of the data sheet.
4 Revision History
Changes from B Revision (November 2015) to C Revision
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Changed Figure 45: changed capacitor values from 820 nF to 820 pF Go
Changes from A Revision (October 2011) to B Revision
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Added ESD Ratings table, Recommended Operating Conditions table, Feature Description section, Device Functional Modes section, Register Maps section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information sectionGo
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Changed title of Device Comparison Table, deleted footnote 1 Go
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Added Storage temperature parameter to Absolute Maximum Ratings tableGo
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Changed Clock cycles per conversion to be a single parameter instead of part of tCONV parameter in Serial Interface Timing Requirements table Go
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Changed tBUFS parameter in Serial Interface Timing Requirements tableGo
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Added footnote 3 to Serial Interface Timing Requirements tableGo
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Changed Clock cycles per conversion to be a single parameter instead of part of tCONV parameter in Parallel Interface Timing Requirements (Read Access) table Go
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Changed tBUCS parameter in Parallel Interface Timing Requirements (Read Access) table Go
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Added footnote 3 to Parallel Interface Timing Requirements (Read Access) table Go
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Changed Data Readout and BUSY/INT Signal sectionGo
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Added Sequential Operation sectionGo
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Changed description of initiating a new conversion in Reset and Power-Down Modes sectionGo
Changes from * Revision (August 2011) to A Revision
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Deleted INL column from Family/Ordering Information tableGo
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Changed DC Accuracy, INL parameter in ADS8568 Electical Chatacteristics tableGo