SBAS656B September   2015  – April 2016 ADS1257

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Serial Interface Timing Requirements
    7. 7.7  Serial Interface Switching Characteristics
    8. 7.8  RESET and SYNC/PWDN Timing Requirements
    9. 7.9  SCLK Reset Timing Requirements
    10. 7.10 DRDY Update Timing Characteristics
    11. 7.11 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Noise Performance
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Input Multiplexer
      2. 9.3.2  Analog Input Buffer
      3. 9.3.3  Programmable Gain Amplifier (PGA)
      4. 9.3.4  Modulator Input Circuitry
      5. 9.3.5  Voltage Reference Inputs (REFP, REFN)
      6. 9.3.6  Clock Input (CLKIN)
      7. 9.3.7  Clock Output (D0/CLKOUT)
      8. 9.3.8  General-Purpose Digital I/O (D0, D1)
      9. 9.3.9  Open- and Short-Circuit Sensor Detection
      10. 9.3.10 Digital Filter
        1. 9.3.10.1 Frequency Response
        2. 9.3.10.2 50-Hz and 60-Hz, Line Cycle Rejection
        3. 9.3.10.3 Settling Time
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-Up
      2. 9.4.2 Reset
      3. 9.4.3 Standby Mode
      4. 9.4.4 Power-Down Mode
      5. 9.4.5 Conversion Control and Synchronization
        1. 9.4.5.1 Settling Time Using Synchronization
        2. 9.4.5.2 Settling Time Using Single-Shot Mode
        3. 9.4.5.3 Settling Time Using the Input Multiplexer
        4. 9.4.5.4 Settling Time while Continuously Converting
      6. 9.4.6 Calibration
        1. 9.4.6.1 Self-Calibration
          1. 9.4.6.1.1 SELFOCAL Command: Self-Offset Calibration
          2. 9.4.6.1.2 SELFGCAL Command: Self-Gain Calibration
          3. 9.4.6.1.3 SELFCAL Command: Self-Offset and Self-Gain Calibration
        2. 9.4.6.2 System Calibration
          1. 9.4.6.2.1 SYSOCAL Command: System-Offset Calibration
          2. 9.4.6.2.2 SYSGCAL Command: System-Gain Calibration
        3. 9.4.6.3 Auto-Calibration
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Chip Select (CS)
        2. 9.5.1.2 Serial Clock (SCLK)
        3. 9.5.1.3 Data Input (DIN) and Data Output (DOUT)
        4. 9.5.1.4 Data Ready (DRDY)
      2. 9.5.2 Data Format
      3. 9.5.3 Command Definitions
        1. 9.5.3.1  WAKEUP/NOP: Complete Synchronization or Exit Standby Mode
        2. 9.5.3.2  RDATA: Read Data
        3. 9.5.3.3  RDATAC: Read Data Continuous
        4. 9.5.3.4  SDATAC: Stop Read Data Continuous
        5. 9.5.3.5  RREG: Read from Registers
        6. 9.5.3.6  WREG: Write to Register
        7. 9.5.3.7  SELFCAL: Self-Offset and Self-Gain Calibration
        8. 9.5.3.8  SELFOCAL: Self Offset Calibration
        9. 9.5.3.9  SELFGCAL: Self Gain Calibration
        10. 9.5.3.10 SYSOCAL: System Offset Calibration
        11. 9.5.3.11 SYSGCAL: System Gain Calibration
        12. 9.5.3.12 STANDBY: Standby Mode / Single-shot Mode
        13. 9.5.3.13 RESET: Reset Registers to Default Values
        14. 9.5.3.14 SYNC: Synchronize the Analog-to-Digital Conversion
    6. 9.6 Register Map
      1. 9.6.1  STATUS: Status Register (address = 00h) [reset = x1h]
      2. 9.6.2  MUX : Input Multiplexer Control Register (address = 01h) [reset = 01h]
      3. 9.6.3  ADCON: ADC Control Register (address = 02h) [reset = 20h]
      4. 9.6.4  DRATE: ADC Data Rate Register (address = 03h) [reset = F0h]
      5. 9.6.5  IO: GPIO Control Register (address = 04h) [reset = E0h]
      6. 9.6.6  OFC0: Offset Calibration Register 0 (address = 05h) [reset = depends on calibration results]
      7. 9.6.7  OFC1: Offset Calibration Register 1 (address = 06h) [reset = depends on calibration results]
      8. 9.6.8  OFC2: Offset Calibration Register 2 (address = 07h) [reset = depends on calibration results]
      9. 9.6.9  FSC0: Full-Scale Calibration Register 0 (address = 08h) [reset = depends on calibration results]
      10. 9.6.10 FSC1: Full-Scale Calibration Register 1 (address = 09h) [reset = depends on calibration results]
      11. 9.6.11 FSC2: Full-Scale Calibration Register 2 (address = 0Ah) [reset = depends on calibration results]
  10. 10Applications and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Basic Connections
      2. 10.1.2 Digital Interface Connections
      3. 10.1.3 Analog Input Filtering
      4. 10.1.4 External Reference
      5. 10.1.5 Isolated (or Floating) Sensor Inputs
      6. 10.1.6 Unused Inputs and Outputs
      7. 10.1.7 Pseudo Code Example
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Detailed Design Procedure for ±10-V Input
          1. 10.2.2.1.1 Absolute Input Voltage Range
          2. 10.2.2.1.2 Differential Input Voltage Range
          3. 10.2.2.1.3 Level-Shifted Resistor Divider Sizing
          4. 10.2.2.1.4 Input Filtering
          5. 10.2.2.1.5 Register Settings for ±10-V Input
          6. 10.2.2.1.6 Voltage Input Design Variations
        2. 10.2.2.2 Detailed Design Procedure for 4-mA to 20-mA Input
          1. 10.2.2.2.1 PGA Gain Selection
          2. 10.2.2.2.2 Current-Sense Resistor Sizing
          3. 10.2.2.2.3 Register Settings for 4-mA to 20-mA Input
          4. 10.2.2.2.4 Current Input Design Variations
      3. 10.2.3 Application Curves
    3. 10.3 Dos and Don'ts
  11. 11Power Supply Recommendations
    1. 11.1 Power-Supply Sequencing
    2. 11.2 Power-Supply Decoupling
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Up to 23-Bits Noise-Free Resolution
  • Small 5-mm × 5-mm VQFN Package
  • 4 Analog Inputs
    • 2 Differential or 3 Single-Ended Measurements
  • Excellent DC Performance
    • Offset Drift: 4 nV/°C (Gain = 64)
    • Gain Drift: 0.8 ppm/°C
    • Nonlinearity: 3 ppm (Gain = 1)
  • Programmable Data Rates: 2.5 SPS to 30 kSPS
  • Single-Cycle Settled Conversions (≤ 1000 SPS)
  • 50-Hz and 60-Hz Rejection
  • High Impedance Input Buffer
  • Differential-Input PGA
  • Integrated Sensor Break Detection
  • 2 General-Purpose Input/Outputs
  • Power Supplies:
    • Analog: 5 V
    • Digital: 1.8 V to 3.6 V
  • 5-V Tolerant SPI™-Compatible Serial Interface

2 Applications

  • Factory Automation and Process Control
  • Test and Measurement
  • Medical Equipment
  • Scientific Instrumentation

3 Description

The ADS1257 is a low-noise, 30-kSPS, 24-bit, delta-sigma (ΔΣ) analog-to-digital converter (ADC) with an integrated multiplexer (mux), input buffer, and programmable gain amplifier (PGA) in a small 20-pin, 5-mm × 5-mm VQFN package. The combination of integration, high conversion rate, and 24-bit resolution together in a small package makes the device ideally suited for space-constrained applications.

The input multiplexer accepts either two differential or three single-ended input measurements. The sensor-break detection circuit verifies the input connection continuity to the ADC. The selectable input buffer greatly increases the input impedance, and in many cases, eliminates the need for external buffers. The buffer input voltage range includes AGND. The low-noise PGA provides gains from 1 to 64 to accommodate a wide range of inputs signals. The programmable digital filter optimizes ADC resolution (up to 23 bits noise-free) and conversion rates (up to 30 kSPS). The digital filter provides single-cycle settled conversions, and rejection of 50-Hz and 60-Hz interference signals.

The SPI-compatible serial interface operates with as little as three wires, simplifying connections to external controllers. Integrated calibration features support both self and system correction of offset and gain errors for all PGA gain settings. Two bidirectional digital I/Os pins control external circuits.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
ADS1257 VQFN (20) 5.00 mm × 5.00 mm
  1. For all available packages, see the package option addendum at the end of the data sheet.

Block Diagram

ADS1257 pg1_fbd_bas656.gif

Output Data Histogram
(256 Readings, 2.5 SPS, Gain = 1)

ADS1257 tc_histo_noise_pga1_25sps_bas656.gif