SLUSCJ9E
June 2016 – December 2021
UCC21520
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Description (continued)
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Power Ratings
7.6
Insulation Specifications
7.7
Safety-Related Certifications
7.8
Safety-Limiting Values
7.9
Electrical Characteristics
7.10
Switching Characteristics
7.11
Insulation Characteristics Curves
7.12
Typical Characteristics
8
Parameter Measurement Information
8.1
Propagation Delay and Pulse Width Distortion
8.2
Rising and Falling Time
8.3
Input and Disable Response Time
8.4
Programable Dead Time
8.5
Power-up UVLO Delay to OUTPUT
8.6
CMTI Testing
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
VDD, VCCI, and Undervoltage Lock Out (UVLO)
9.3.2
Input and Output Logic Table
9.3.3
Input Stage
9.3.4
Output Stage
9.3.5
Diode Structure in the UCC21520 and the UCC21520A
9.4
Device Functional Modes
9.4.1
Disable Pin
9.4.2
Programmable Dead-Time (DT) Pin
9.4.2.1
Tying the DT Pin to VCC
9.4.2.2
DT Pin Connected to a Programming Resistor between DT and GND Pins
9.4.2.3
41
10
Application and Implementation
10.1
Application Information
10.2
Typical Application
10.2.1
Design Requirements
10.2.2
Detailed Design Procedure
10.2.2.1
Designing INA/INB Input Filter
10.2.2.2
Select External Bootstrap Diode and its Series Resistor
10.2.2.3
Gate Driver Output Resistor
10.2.2.4
Gate to Source Resistor Selection
10.2.2.5
Estimate Gate Driver Power Loss
10.2.2.6
Estimating Junction Temperature
10.2.2.7
Selecting VCCI, VDDA/B Capacitor
10.2.2.7.1
Selecting a VCCI Capacitor
10.2.2.7.2
Selecting a VDDA (Bootstrap) Capacitor
10.2.2.7.3
Select a VDDB Capacitor
10.2.2.8
Dead Time Setting Guidelines
10.2.2.9
Application Circuits with Output Stage Negative Bias
10.2.3
Application Curves
11
Power Supply Recommendations
12
Layout
12.1
Layout Guidelines
12.2
Layout Example
13
Device and Documentation Support
13.1
Third-Party Products Disclaimer
13.2
Documentation Support
13.2.1
Related Documentation
13.3
Certifications
13.4
Receiving Notification of Documentation Updates
13.5
Support Resources
13.6
Trademarks
13.7
Electrostatic Discharge Caution
13.8
Glossary
14
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DW|16
MSOI003I
Thermal pad, mechanical data (Package|Pins)
DW|16
QFND505A
Orderable Information
sluscj9e_oa
sluscj9e_pm
1
Features
Universal: dual low-side, dual high-side or half-bridge driver
Operating temperature range –40 to +125°C
Switching parameters:
19-ns typical propagation delay
10-ns minimum pulse width
5-ns maximum delay matching
6
-ns maximum pulse-width distortion
Common-mode transient immunity (CMTI) greater than 100 V/ns
Surge immunity up to 12.8 kV
Isolation barrier life >40 years
4-A peak source, 6-A peak sink output
TTL and CMOS compatible inputs
3-V to 18-V input VCCI range to interface with both digital and analog controllers
Up to 25-V VDD output drive supply
5-V and 8-V VDD UVLO options
Programmable overlap and dead time
Rejects input pulses and noise transients shorter than 5 ns
Fast disable for power sequencing
Industry standard wide body SOIC-16 (DW) package
Safety-related certifications:
8000-V
PK
reinforced Isolation per DIN V VDE V 0884-11:2017-01
5.7-kV
RMS
isolation for 1 minute per UL 1577
CSA certification per IEC 60950-1, IEC 62368-1, IEC 61010-1 and IEC 60601-1 end equipment standards
CQC certification per GB4943.1-2011