SLUSCV6A
April 2017 – February 2018
UCC21225A
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Device Images
Functional Block Diagram
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Power Ratings
6.6
Insulation Specifications
6.7
Safety-Related Certifications
6.8
Safety-Limiting Values
6.9
Electrical Characteristics
6.10
Switching Characteristics
6.11
Insulation Characteristics and Thermal Derating Curves
6.12
Typical Characteristics
7
Parameter Measurement Information
7.1
Propagation Delay and Pulse Width Distortion
7.2
Rising and Falling Time
7.3
Input and Disable Response Time
7.4
Programable Dead Time
7.5
Power-up UVLO Delay to OUTPUT
7.6
CMTI Testing
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
VDD, VCCI, and Under Voltage Lock Out (UVLO)
8.3.2
Input and Output Logic Table
8.3.3
Input Stage
8.3.4
Output Stage
8.3.5
Diode Structure in UCC21225A
8.4
Device Functional Modes
8.4.1
Disable Pin
8.4.2
Programmable Dead Time (DT) Pin
8.4.2.1
Tying the DT Pin to VCC
8.4.2.2
DT Pin Left Open or Connected to a Programming Resistor between DT and GND Pins
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Designing INA/INB Input Filter
9.2.2.2
Select External Bootstrap Diode and Series Resistor
9.2.2.3
Gate Driver Output Resistor
9.2.2.4
Estimate Gate Driver Power Loss
9.2.2.5
Estimating Junction Temperature
9.2.2.6
Selecting VCCI, VDDA/B Capacitor
9.2.2.6.1
Selecting a VCCI Capacitor
9.2.2.6.2
Selecting a VDDA (Bootstrap) Capacitor
9.2.2.6.3
Select a VDDB Capacitor
9.2.2.7
Dead Time Setting Guidelines
9.2.2.8
Application Circuits with Output Stage Negative Bias
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Documentation Support
12.1.1
Related Documentation
12.2
Certifications
12.2.1
Receiving Notification of Documentation Updates
12.3
Community Resources
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
NPL|13
MPLG063A
Thermal pad, mechanical data (Package|Pins)
Orderable Information
sluscv6a_oa
sluscv6a_pm
1
Features
Universal: Dual Low-Side, Dual High-Side or Half-Bridge Driver
5 x 5 mm, Space-Saving LGA-13 Package
Switching Parameters:
19-ns Typical Propagation Delay
5-ns Maximum Delay Matching
6-ns Maximum Pulse-Width Distortion
CMTI Greater than 100-V/ns
4-A Peak Source, 6-A Peak Sink Output
TTL and CMOS Compatible Inputs
3-V to 18-V Input VCCI Range
Up to 25-V VDD with 5-V UVLO
Programmable Overlap and Dead Time
Rejects Input Transients Shorter than 5-ns
Fast Disable for Power Sequencing
Safety-Related Certifications:
3535-V
PK
Isolation per DIN V VDE V 0884-11:2017-01
2500-V
RMS
Isolation for 1 Minute per UL 1577
CQC per GB4943.1-2011
(Planned)