SBVS128F June   2009  – December 2015 TPS727

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configurations and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Internal Current Limit
      2. 7.3.2 Soft Start
      3. 7.3.3 Shutdown
      4. 7.3.4 Dropout Voltage
      5. 7.3.5 Undervoltage Lock-out (UVLO)
      6. 7.3.6 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation with EN Control
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Input and Output Capacitor Requirements
        2. 8.2.1.2 Transient Response
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power-Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
      2. 10.1.2 Power Dissipation
      3. 10.1.3 Package Mounting
    2. 10.2 Layout Example
      1. 10.2.1 DSE EVM Board Layout
      2. 10.2.2 YFF EVM Board Layout
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
      2. 11.1.2 Device Nomenclature
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YFF|4
  • DSE|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Very Low Dropout:
    • 65 mV Typical at 100 mA
    • 130 mV Typical at 200 mA
    • 163 mV Typical at 250 mA
  • 2% Accuracy Over Load, Line, Temperature
  • Ultralow IQ: 7.9 μA
  • Excellent Load Transient Performance:±50 mV for 200 mA Loading and Unloading Transient
  • Available in Fixed-Output Voltages From 0.9 V to 5 V Using Innovative Factory EEPROM Programming
  • High PSRR: 70 dB at 1 kHz
  • Stable with a 1.0-μF Ceramic Capacitor
  • Thermal Shutdown and Overcurrent Protection
  • Available in 4-Ball, 0.4-mm Pitch Wafer-Level Chip Scale and 1.5-mm × 1.5-mm SON Packages

2 Applications

  • Wireless Handsets, Smart Phones, PDAs
  • MP3 Players and Other Handheld Products
  • Wireless LAN, Bluetooth®, Zigbee®
  • Remote Controls
  • Portable Consumer Products

3 Description

The TPS727 family of low-dropout (LDO) linear regulators are ultralow quiescent current LDOs with excellent line and ultra-fast load transient performance and are designed for power-sensitive applications. The LDO output voltage level is preset by the use of innovative factory EEPROM programming. A precision band-gap and error amplifier provides overall 2% accuracy over load, line, and temperature extremes. The TPS727 family is available in 1.5-mm × 1.5-mm SON and wafer chip-scale (WCSP) packages that make the devices ideal for handheld applications. This family of devices is fully specified over a temperature range of TJ = –40°C to +125°C.

Device Information

PART NUMBER PACKAGE BODY SIZE (NOM)
TPS727xxDSE WSON (6) 1.50 mm × 1.50 mm
TPS727xxYFF DSBGA (4) 1.20 mm × 0.80 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.
TPS727 fp_all_bvs128.gif

4 Revision History

Changes from E Revision (September 2014) to F Revision

  • Changed DSBGA body size in Device Information table Go

Changes from D Revision (February 2014) to E Revision

  • Added TPS727105 to documentGo
  • Changed terminal to pin throughout documentGo
  • Updated Device Information table to current standardsGo
  • Changed Pin Configurations note Go
  • Changed Pin Functions table: reordered table by pin name, added I/O columnGo
  • Updated Handling Ratings table to current standardGo
  • Changed Thermal Information table: updated symbolsGo
  • Deleted new generation from first sentence of Overview sectionGo
  • Added note to Applications and Implementation sectionGo

Changes from C Revision (January, 2011) to D Revision

  • Changed format to meet latest data sheet standards; added new sections and moved existing sectionsGo
  • Deleted pinout diagrams from front page; see Pin Configurations and Functions section.Go
  • Changed Pin Configurations section and moved to Pin Configurations and Functions sectionGo
  • Changed note in Pin Configurations and Functions section.Go
  • Deleted Figure 26 and Figure 27Go

Changes from B Revision (April, 2010) to C Revision

  • Updated YFF front page pin drawing to show pin locationsGo
  • Revised Pin Configurations section Go
  • Changed graph title for Figure 6Go

Changes from A Revision (September, 2009) to B Revision