SLVS932F May   2009  – November 2014 TPS54325

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Thermal Information
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Soft Start and Pre-Biased Soft Start
      2. 8.3.2 Power Good
      3. 8.3.3 Output Discharge Control
      4. 8.3.4 Current Protection
      5. 8.3.5 Overvoltage and Undervoltage Protection
      6. 8.3.6 UVLO Protection
      7. 8.3.7 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 PWM Operation
      2. 8.4.2 PWM Frequency and Adaptive On-Time Control
      3. 8.4.3 Operation with VIN < 4.5 V
      4. 8.4.4 Operation With EN Control
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Voltage Resistors Selection
        2. 9.2.2.2 Output Filter Selection
        3. 9.2.2.3 Input Capacitor Selection
        4. 9.2.2.4 Bootstrap Capacitor Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • D-CAP2™ Mode Enables Fast Transient Response
  • Low Output Ripple and Allows Ceramic Output Capacitor
  • Wide VCC Input Voltage Range: 4.5 V to 18 V
  • Wide VIN Input Voltage Range: 2.0 V to 18 V
  • Output Voltage Range: 0.76 V to 5.5 V
  • Highly Efficient Integrated FET’s Optimized for Lower Duty Cycle Applications – 120 mΩ (High Side) and 70 mΩ (Low Side)
  • High Efficiency, less than 10 μA at shutdown
  • High Initial Bandgap Reference Accuracy
  • Adjustable Soft Start
  • Pre-Biased Soft Start
  • 700-kHz Switching Frequency (fSW)
  • Cycle By Cycle Over Current Limit
  • Power Good Output

2 Applications

  • Wide Range of Applications for Low Voltage System
    • Digital TV Power Supply
    • High Definition Blu-ray Disc™ Players
    • Networking Home Terminal
    • Digital Set Top Box (STB)

3 Description

The TPS54325 device is an adaptive on-time D-CAP2™ mode synchronous buck converter. The TPS54325 device enables system designers to complete the suite of various end equipment’s power bus regulators with a cost effective, low component count, low standby current solution.

The main control loop for the TPS54325 uses the D-CAP2™ mode control which provides a very fast transient response with no external components. The TPS54325 also has a proprietary circuit that enables the device to adapt to both low equivalent series resistance (ESR) output capacitors, such as POSCAP or SP-CAP, and ultra-low ESR ceramic capacitors. The device operates from 4.5-V to 18-V VCC input , and from 2.0-V to 18-V VIN input power supply voltage. The output voltage can be programmed between 0.76 V and 5.5 V. The device also features an adjustable slow start time and a power good function. The TPS54325 is available in the 14 pin HTSSOP package, and designed to operate from –40°C to 85°C.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TPS54325 HTSSOP (14) 5.00 mm × 4.40 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

4 Simplified Schematic

sch1_lvs932.gif

Load Transient Response

load1_lvs932.gif