1 Features

• AEC-Q100 Qualified With the Following Results:
  • Device Temperature Grade 1: –40°C to +125°C Ambient Operating Temperature Range
  • Device HBM ESD Classification Level 2
  • Device CDM ESD Classification Level C6
• Single-chip DDR2, DDR3 and DDR3L Memory Power Solution
• 4-A Synchronous Buck Converter
  • Integrated 33-mΩ High-side and 25-mΩ Low-side MOSFETs
  • Fixed Frequency Current-mode Control
  • Adjustable Frequency from 100 kHz to 2.5 MHz
  • Synchronizable to an External Clock
  • 0.6-V ±1% Voltage Reference Over Temperature
  • Adjustable Cycle-by-Cycle Peak Current Limit
  • Monotonic Start-up Into Pre-biased Outputs
• 1-A Source/Sink Termination LDO with ±20-mV DC Accuracy
  • Stable with 2 × 10-µF MLCC Capacitor
  • 10-mA Source/Sink Buffered Reference Output Regulated to Within 49% to 51% of VDDQ
• Independent Enable Pins with Adjustable UVLO and Hysteresis
• Thermal Shutdown
• -40°C to 150°C Operating T_J
• 24-pin, 4-mm x 4-mm WQFN Package

2 Applications

• DDR2, DDR3, DDR3L, and DDR4 Memory Power Supplies in Embedded Computing Systems
• SSTL_18, SSTL_15, SSTL_135, SSTL_12 and HSTL Termination
• Infotainment and Cluster
• Advanced Driver Assistance Systems (ADAS)

3 Description

The TPS54116-Q1 device is a full featured 6-V, 4-A, synchronous step down converter with two integrated MOSFETs and 1-A sink/source double data rate (DDR) VTT termination regulator with VTTREF buffered reference output.

The TPS54116-Q1 buck regulator minimizes solution size by integrating the MOSFETs and reducing inductor size with up to 2.5-MHz switching frequency. The switching frequency can be set above the medium wave radio band for noise sensitive applications and is synchronizable to an external clock. Synchronous rectification keeps the frequency fixed across the entire output load range. Efficiency is maximized through integrated 25-mΩ low-side and 33-mΩ high-side MOSFETs. Cycle-by-cycle peak current limit protects the device during an overcurrent condition and is adjustable with a resistor at the ILIM pin to optimize for smaller inductors.

The VTT termination regulator maintains fast transient response with only 2 × 10-µF ceramic output capacitance reducing external component count. The TPS54116-Q1 uses remote sensing of VTT for best regulation.

Using the enable pins to enter a shutdown mode reduces supply current to 1-µA. Under voltage lockout thresholds can be set with a resistor network on either enable pin. The VTT and VTTREF outputs are discharged when disabled with ENLDO.

Full integration minimizes the IC footprint with a small 4 mm × 4 mm thermally enhanced WQFN package.

1. For all available packages, see the orderable addendum at the end of the datasheet.

Simplified Schematic

4 Revision History

Changes from A Revision (August 2016) to B Revision

• Changed text From: "double date rate (DDR)" To: "double data rate (DDR)" in the DescriptionGo

Changes from * Revision (August 2016) to A Revision

• Changed pin 18 From: RT/CLK To: RT/SYNC in the Pin Functions tableGo
• Changed R_(RT/CLK) To: R_(RT/SYNC) in Figure 16 and Figure 17Go
• Changed "The RT/CLK is typically 0.5 V.." To: "The RT/SYNC is typically 0.5 V.." in Constant Switching Frequency and Timing Resistor (RT/SYNC)Go