SPRSP19 December   2017 TMS320F28377D-EP

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Terminal Configuration and Functions
    1. 3.1 Pin Diagrams
    2. 3.2 Signal Descriptions
    3. 3.3 Pins With Internal Pullup and Pulldown
    4. 3.4 Pin Multiplexing
      1. 3.4.1 GPIO Muxed Pins
      2. 3.4.2 Input X-BAR
      3. 3.4.3 Output X-BAR and ePWM X-BAR
      4. 3.4.4 USB Pin Muxing
      5. 3.4.5 High-Speed SPI Pin Muxing
    5. 3.5 Connections for Unused Pins
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Power Consumption Summary
      1. 4.4.1 Current Consumption Graphs
      2. 4.4.2 Reducing Current Consumption
    5. 4.5  Electrical Characteristics
    6. 4.6  Thermal Resistance Characteristics
      1. 4.6.1 GWT Package
      2. 4.6.2 PTP Package
    7. 4.7  System
      1. 4.7.1 Power Sequencing
      2. 4.7.2 Reset Timing
        1. 4.7.2.1 Reset Sources
        2. 4.7.2.2 Reset Electrical Data and Timing
      3. 4.7.3 Clock Specifications
        1. 4.7.3.1 Clock Sources
        2. 4.7.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 4.7.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
          2. 4.7.3.2.2 Internal Clock Frequencies
          3. 4.7.3.2.3 Output Clock Frequency and Switching Characteristics
        3. 4.7.3.3 Input Clocks and PLLs
        4. 4.7.3.4 Crystal Oscillator
        5. 4.7.3.5 Internal Oscillators
      4. 4.7.4 Flash Parameters
      5. 4.7.5 Emulation/JTAG
        1. 4.7.5.1 JTAG Electrical Data and Timing
      6. 4.7.6 GPIO Electrical Data and Timing
        1. 4.7.6.1 GPIO - Output Timing
        2. 4.7.6.2 GPIO - Input Timing
        3. 4.7.6.3 Sampling Window Width for Input Signals
      7. 4.7.7 Interrupts
        1. 4.7.7.1 External Interrupt (XINT) Electrical Data and Timing
      8. 4.7.8 Low-Power Modes
        1. 4.7.8.1 Clock-Gating Low-Power Modes
        2. 4.7.8.2 Power-Gating Low-Power Modes
        3. 4.7.8.3 Low-Power Mode Wakeup Timing
      9. 4.7.9 External Memory Interface (EMIF)
        1. 4.7.9.1 Asynchronous Memory Support
        2. 4.7.9.2 Synchronous DRAM Support
        3. 4.7.9.3 EMIF Electrical Data and Timing
          1. 4.7.9.3.1 Asynchronous RAM
          2. 4.7.9.3.2 Synchronous RAM
    8. 4.8  Analog Peripherals
      1. 4.8.1 Analog-to-Digital Converter (ADC)
        1. 4.8.1.1 ADC Electrical Data and Timing
          1. 4.8.1.1.1 ADC Input Models
          2. 4.8.1.1.2 ADC Timing Diagrams
        2. 4.8.1.2 Temperature Sensor Electrical Data and Timing
      2. 4.8.2 Comparator Subsystem (CMPSS)
        1. 4.8.2.1 CMPSS Electrical Data and Timing
      3. 4.8.3 Buffered Digital-to-Analog Converter (DAC)
        1. 4.8.3.1 Buffered DAC Electrical Data and Timing
    9. 4.9  Control Peripherals
      1. 4.9.1 Enhanced Capture (eCAP)
        1. 4.9.1.1 eCAP Electrical Data and Timing
      2. 4.9.2 Enhanced Pulse Width Modulator (ePWM)
        1. 4.9.2.1 Control Peripherals Synchronization
        2. 4.9.2.2 ePWM Electrical Data and Timing
          1. 4.9.2.2.1 Trip-Zone Input Timing
        3. 4.9.2.3 External ADC Start-of-Conversion Electrical Data and Timing
      3. 4.9.3 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 4.9.3.1 eQEP Electrical Data and Timing
      4. 4.9.4 High-Resolution Pulse Width Modulator (HRPWM)
        1. 4.9.4.1 HRPWM Electrical Data and Timing
      5. 4.9.5 Sigma-Delta Filter Module (SDFM)
        1. 4.9.5.1 SDFM Electrical Data and Timing
    10. 4.10 Communications Peripherals
      1. 4.10.1 Controller Area Network (CAN)
      2. 4.10.2 Inter-Integrated Circuit (I2C)
        1. 4.10.2.1 I2C Electrical Data and Timing
      3. 4.10.3 Multichannel Buffered Serial Port (McBSP)
        1. 4.10.3.1 McBSP Electrical Data and Timing
          1. 4.10.3.1.1 McBSP Transmit and Receive Timing
          2. 4.10.3.1.2 McBSP as SPI Master or Slave Timing
      4. 4.10.4 Serial Communications Interface (SCI)
      5. 4.10.5 Serial Peripheral Interface (SPI)
        1. 4.10.5.1 SPI Electrical Data and Timing
          1. 4.10.5.1.1 Non-High-Speed Master Mode Timings
          2. 4.10.5.1.2 Non-High-Speed Slave Mode Timings
          3. 4.10.5.1.3 High-Speed Master Mode Timings
          4. 4.10.5.1.4 High-Speed Slave Mode Timings
      6. 4.10.6 Universal Serial Bus (USB) Controller
        1. 4.10.6.1 USB Electrical Data and Timing
      7. 4.10.7 Universal Parallel Port (uPP) Interface
        1. 4.10.7.1 uPP Electrical Data and Timing
  5. 5Detailed Description
    1. 5.1  Overview
    2. 5.2  Functional Block Diagram
    3. 5.3  Memory
      1. 5.3.1 C28x Memory Map
      2. 5.3.2 Flash Memory Map
      3. 5.3.3 EMIF Chip Select Memory Map
      4. 5.3.4 Peripheral Registers Memory Map
      5. 5.3.5 Memory Types
        1. 5.3.5.1 Dedicated RAM (Mx and Dx RAM)
        2. 5.3.5.2 Local Shared RAM (LSx RAM)
        3. 5.3.5.3 Global Shared RAM (GSx RAM)
        4. 5.3.5.4 CPU Message RAM (CPU MSGRAM)
        5. 5.3.5.5 CLA Message RAM (CLA MSGRAM)
    4. 5.4  Identification
    5. 5.5  Bus Architecture - Peripheral Connectivity
    6. 5.6  C28x Processor
      1. 5.6.1 Floating-Point Unit
      2. 5.6.2 Trigonometric Math Unit
      3. 5.6.3 Viterbi, Complex Math, and CRC Unit II (VCU-II)
    7. 5.7  Control Law Accelerator
    8. 5.8  Direct Memory Access
    9. 5.9  Interprocessor Communication Module
    10. 5.10 Boot ROM and Peripheral Booting
      1. 5.10.1 EMU Boot or Emulation Boot
      2. 5.10.2 WAIT Boot Mode
      3. 5.10.3 Get Mode
      4. 5.10.4 Peripheral Pins Used by Bootloaders
    11. 5.11 Dual Code Security Module
    12. 5.12 Timers
    13. 5.13 Nonmaskable Interrupt With Watchdog Timer (NMIWD)
    14. 5.14 Watchdog
    15. 5.15 Configurable Logic Block (CLB)
  6. 6Applications, Implementation, and Layout
    1. 6.1 TI Design or Reference Design
  7. 7Device and Documentation Support
    1. 7.1 Device and Development Support Tool Nomenclature
    2. 7.2 Tools and Software
    3. 7.3 Device Nomenclature
    4. 7.4 Documentation Support
    5. 7.5 Community Resources
    6. 7.6 Trademarks
    7. 7.7 Electrostatic Discharge Caution
    8. 7.8 Export Control Notice
    9. 7.9 Glossary
  8. 8Mechanical, Packaging, and Orderable Information
    1. 8.1 Via Channel
    2. 8.2 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Device Overview

1.1 Features

  • Dual-Core Architecture
    • Two TMS320C28x 32-Bit CPUs
    • 200 MHz
    • IEEE 754 Single-Precision Floating-Point Unit (FPU)
    • Trigonometric Math Unit (TMU)
    • Viterbi/Complex Math Unit (VCU-II)
  • Two Programmable Control Law Accelerators (CLAs)
    • 200 MHz
    • IEEE 754 Single-Precision Floating-Point Instructions
    • Executes Code Independently of Main CPU
  • On-Chip Memory
    • 512KB (256KW) or 1MB (512KW) of Flash (ECC-Protected)
    • 172KB (86KW) or 204KB (102KW) of RAM (ECC-Protected or Parity-Protected)
    • Dual-Zone Security Supporting Third-Party Development
  • Clock and System Control
    • Two Internal Zero-Pin 10-MHz Oscillators
    • On-Chip Crystal Oscillator
    • Windowed Watchdog Timer Module
    • Missing Clock Detection Circuitry
  • 1.2-V Core, 3.3-V I/O Design
  • System Peripherals
    • Two External Memory Interfaces (EMIFs) With ASRAM and SDRAM Support
    • Dual 6-Channel Direct Memory Access (DMA) Controllers
    • Up to 169 Individually Programmable, Multiplexed General-Purpose Input/Output (GPIO) Pins With Input Filtering
    • Expanded Peripheral Interrupt Controller (ePIE)
    • Multiple Low-Power Mode (LPM) Support With External Wakeup
  • Communications Peripherals
    • USB 2.0 (MAC + PHY)
    • Support for 12-Pin 3.3 V-Compatible Universal Parallel Port (uPP) Interface
    • Two Controller Area Network (CAN) Modules (Pin-Bootable)
    • Three High-Speed (up to 50-MHz) SPI Ports (Pin-Bootable)
    • Two Multichannel Buffered Serial Ports (McBSPs)
    • Four Serial Communications Interfaces (SCI/UART) (Pin-Bootable)
    • Two I2C Interfaces (Pin-Bootable)
  • Analog Subsystem
    • Up to Four Analog-to-Digital Converters (ADCs)
      • 16-Bit Mode
        • 1.1 MSPS Each (up to 4.4-MSPS System Throughput)
        • Differential Inputs
        • Up to 12 External Channels
      • 12-Bit Mode
        • 3.5 MSPS Each (up to 14-MSPS System Throughput)
        • Single-Ended Inputs
        • Up to 24 External Channels
      • Single Sample-and-Hold (S/H) on Each ADC
      • Hardware-Integrated Post-Processing of ADC Conversions
        • Saturating Offset Calibration
        • Error From Setpoint Calculation
        • High, Low, and Zero-Crossing Compare, With Interrupt Capability
        • Trigger-to-Sample Delay Capture
    • Eight Windowed Comparators With 12-Bit Digital-to-Analog Converter (DAC) References
    • Three 12-Bit Buffered DAC Outputs
  • Enhanced Control Peripherals
    • 24 Pulse Width Modulator (PWM) Channels With Enhanced Features
    • 16 High-Resolution Pulse Width Modulator (HRPWM) Channels
      • High Resolution on Both A and B Channels of 8 PWM Modules
      • Dead-Band Support (on Both Standard and High Resolution)
    • Six Enhanced Capture (eCAP) Modules
    • Three Enhanced Quadrature Encoder Pulse (eQEP) Modules
    • Eight Sigma-Delta Filter Module (SDFM) Input Channels, 2 Parallel Filters per Channel
      • Standard SDFM Data Filtering
      • Comparator Filter for Fast Action for Out of Range
  • Package Options:
    • 337-Ball New Fine Pitch Ball Grid Array (nFBGA) [GWT Suffix]
    • 176-Pin PowerPAD™ Thermally Enhanced Low-Profile Quad Flatpack (HLQFP) [PTP Suffix]
  • Supports Defense, Aerospace, and Medical Applications:
    • Controlled Baseline
    • One Assembly/Test Site
    • One Fabrication Site
    • Available in Extended (–55°C to 125°C) Temperature Range
    • Extended Product Life Cycle
    • Extended Product-Change Notification
    • Product Traceability

1.2 Applications

1.3 Description

The Delfino™ TMS320F28377D-EP is a powerful 32-bit floating-point microcontroller unit (MCU) designed for advanced closed-loop control applications such as industrial drives and servo motor control; solar inverters and converters; digital power; transportation; and power line communications. Complete development packages for digital power and industrial drives are available as part of the powerSUITE and DesignDRIVE initiatives. While the Delfino product line is not new to the TMS320C2000™ portfolio, the F28377D supports a new dual-core C28x architecture that significantly boosts system performance. The integrated analog and control peripherals also let designers consolidate control architectures and eliminate multiprocessor use in high-end systems.

The dual real-time control subsystems are based on TI’s 32-bit C28x floating-point CPUs, which provide 200 MHz of signal processing performance in each core. The C28x CPUs are further boosted by the new TMU accelerator, which enables fast execution of algorithms with trigonometric operations common in transforms and torque loop calculations; and the VCU accelerator, which reduces the time for complex math operations common in encoded applications.

The F28377D microcontroller features two CLA real-time control coprocessors. The CLA is an independent 32-bit floating-point processor that runs at the same speed as the main CPU. The CLA responds to peripheral triggers and executes code concurrently with the main C28x CPU. This parallel processing capability can effectively double the computational performance of a real-time control system. By using the CLA to service time-critical functions, the main C28x CPU is free to perform other tasks, such as communications and diagnostics. The dual C28x+CLA architecture enables intelligent partitioning between various system tasks. For example, one C28x+CLA core can be used to track speed and position, while the other C28x+CLA core can be used to control torque and current loops.

The TMS320F28377D-EP supports 1MB (512KW) of onboard flash memory with error correction code (ECC) and 204KB (102KW) of SRAM. Two 128-bit secure zones are also available on each CPU for code protection.

Performance analog and control peripherals are also integrated on the F28377D MCU to further enable system consolidation. Four independent 16-bit ADCs provide precise and efficient management of multiple analog signals, which ultimately boosts system throughput. The new sigma-delta filter module (SDFM) works in conjunction with the sigma-delta modulator to enable isolated current shunt measurements. The Comparator Subsystem (CMPSS) with windowed comparators allows for protection of power stages when current limit conditions are exceeded or not met. Other analog and control peripherals include DACs, PWMs, eCAPs, eQEPs, and other peripherals.

Peripherals such as EMIFs, CAN modules (ISO 11898-1/CAN 2.0B-compliant), and a new uPP interface extend the connectivity of the F28377D. The uPP interface is a new feature of the C2000™ MCUs and supports high-speed parallel connection to FPGAs or other processors with similar uPP interfaces. Lastly, a USB 2.0 port with MAC and PHY lets users easily add universal serial bus (USB) connectivity to their application.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE
TMS320F28377D-EP nFBGA (337) 16.0 mm × 16.0 mm
HLQFP (176) 24.0 mm × 24.0 mm
(1) For more information on these devices, see Mechanical Packaging and Orderable Information.

1.4 Functional Block Diagram

Figure 1-1 shows the CPU system and associated peripherals.

TMS320F28377D-EP fbd_prs880.gif Figure 1-1 Functional Block Diagram