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LM27762 Low-Noise Positive and Negative Output Integrated Charge Pump Plus LDO
SNVSAF7B
August 2016 – February 2017
LM27762
PRODUCTION DATA.
CONTENTS
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LM27762 Low-Noise Positive and Negative Output Integrated Charge Pump Plus LDO
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Undervoltage Lockout
7.3.2
Input Current Limit
7.3.3
PFM Operation
7.3.4
Output Discharge
7.3.5
Power Good Output (PGOOD)
7.3.6
Thermal Shutdown
7.4
Device Functional Modes
7.4.1
Shutdown Mode
7.4.2
Enable Mode
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Custom Design With WEBENCH® Tools
8.2.2.2
Positive Low-Dropout Linear Regulator and OUT+ Voltage Setting
8.2.2.3
Charge-Pump Voltage Inverter
8.2.2.4
Negative Low-Dropout Linear Regulator and OUT- Voltage Setting
8.2.2.5
External Capacitor Selection
8.2.2.5.1
Charge-Pump Output Capacitor
8.2.2.5.2
Input Capacitor
8.2.2.5.3
Flying Capacitor
8.2.2.5.4
LDO Output Capacitor
8.2.2.6
Power Dissipation
8.2.3
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Device Support
11.1.1
Development Support
11.1.1.1
Custom Design With WEBENCH® Tools
11.2
Receiving Notification of Documentation Updates
11.3
Community Resources
11.4
Trademarks
11.5
Electrostatic Discharge Caution
11.6
Glossary
12
Mechanical, Packaging, and Orderable Information
IMPORTANT NOTICE
Package Options
Mechanical Data (Package|Pins)
DSS|12
MPDS336C
Thermal pad, mechanical data (Package|Pins)
DSS|12
QFND398B
Orderable Information
snvsaf7b_oa
snvsaf7b_pm
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