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DAC3xJ82 Dual-Channel, 16-Bit, 1.6/2.5 GSPS, Digital-to-Analog Converters with 12.5 Gbps JESD204B Interface
SLASE16B
January 2014 – May 2014
DAC37J82
,
DAC38J82
PRODUCTION DATA.
CONTENTS
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DAC3xJ82 Dual-Channel, 16-Bit, 1.6/2.5 GSPS, Digital-to-Analog Converters with 12.5 Gbps JESD204B Interface
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
Handling Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
DC Electrical Characteristics
6.6
Digital Electrical Characteristics
6.7
AC Electrical Characteristics
6.8
Timing Requirements
6.9
Switching Characteristics
6.10
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Serdes Input
7.3.2
Serdes Rate
7.3.3
Serdes PLL
7.3.4
Serdes Equalizer
7.3.5
JESD204B Descrambler
7.3.6
JESD204B Frame Assembly
7.3.7
Serial Peripheral Interface (SPI)
7.3.8
Multi-Device Synchronization
7.3.9
Input Multiplexer
7.3.10
FIR Filters
7.3.11
Full Complex Mixer
7.3.12
Coarse Mixer
7.3.13
Dithering
7.3.14
Complex Summation
7.3.15
Quadrature Modulation Correction (QMC)
7.3.15.1
Gain and Phase Correction
7.3.15.2
Offset Correction
7.3.16
Group Delay Correction Block
7.3.16.1
Fine Fractional Delay FIR Filter
7.3.16.2
Coarse Fractional Delay FIR Filter
7.3.17
Output Multiplexer
7.3.18
Power Measurement And Power Amplifier Protection
7.3.19
Serdes Test Modes
7.3.20
Error Counter
7.3.21
Eye Scan
7.3.22
JESD204B Pattern Test
7.3.23
Temperature Sensor
7.3.24
Alarm Monitoring
7.3.25
LVPECL Inputs
7.3.26
CMOS Digital Inputs
7.3.27
Reference Operation
7.3.28
Analog Outputs
7.3.29
DAC Transfer Function
7.4
Device Functional Modes
7.4.1
Clocking Modes
7.4.1.1
PLL Bypass Mode
7.4.1.2
PLL Mode
7.4.2
PRBS Test Mode
7.5
Register Map
7.5.1
Register Descriptions
8
Applications and Implementation
8.1
Application Information
8.2
Typical Applications
8.2.1
Low-IF Wideband LTE Transmitter
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.2.1
Data Input Rate
8.2.1.2.2
Intermediate Frequency
8.2.1.2.3
Interpolation
8.2.1.2.4
DAC PLL Setup
8.2.1.2.5
Serdes Lanes
8.2.1.3
Application Performance Plots
8.2.2
Zero-IF Wideband Transmitter
8.2.2.1
Design Requirements
8.2.2.2
Detailed Design Procedure
8.2.2.2.1
Data Input Rate
8.2.2.2.2
Interpolation
8.2.2.2.3
Serdes Lanes
8.2.2.2.4
LO Feedthrough and Sideband Correction
8.2.2.3
Application Performance Plots
8.3
Initialization Set Up
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Examples
11
Device and Documentation Support
11.1
Related Links
11.2
Trademarks
11.3
Electrostatic Discharge Caution
11.4
Glossary
12
Mechanical, Packaging, and Orderable Information
IMPORTANT NOTICE
Package Options
Mechanical Data (Package|Pins)
AAV|144
MPBGAM2C
Thermal pad, mechanical data (Package|Pins)
Orderable Information
slase16b_oa
slase16b_pm
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