SCAS793G June   2005  – August 2017 CDCM7005

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Automatic/Manual Reference Clock Switching
      2. 9.3.2 PLL Lock for Analog and Digital Detect
        1. 9.3.2.1 PLL Lock/Out-of-Lock Definition
        2. 9.3.2.2 Digital vs Analog Lock
      3. 9.3.3 Differential LVPECL Outputs and Single-Ended LVCMOS Outputs
      4. 9.3.4 Frequency Hold-Over Mode
      5. 9.3.5 Charge Pump Preset to VCC_CP/2
      6. 9.3.6 Charge Pump Current Direction
    4. 9.4 Device Functional Modes
    5. 9.5 Programming
      1. 9.5.1 SPI Control Interface
      2. 9.5.2 Functional Description of the Logic
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Application Information on the Clock Generation for Interpolating DACs With the CDCM7005
        1. 10.1.1.1 AC-Coupled Interface to ADC/DAC
      2. 10.1.2 Phase Noise
      3. 10.1.3 In-Band Noise Performance
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGZ|48
  • ZVA|64
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • High Performance LVPECL and LVCMOS PLL Clock Synchronizer
  • Two Reference Clock Inputs (Primary and Secondary Clock) for Redundancy Support With Manual or Automatic Selection
  • Accepts LVCMOS Input Frequencies up to 200 MHz
  • VCXO_IN Clock is Synchronized to One of the Two Reference Clocks
  • VCXO_IN Frequencies Up to 2.2 GHz (LVPECL)
  • Outputs Can Be a Combination of LVPECL and LVCMOS (Up to Five Differential LVPECL Outputs or up to 10 LVCMOS Outputs)
  • Output Frequency is Selectable by ×1, /2, /3, /4, /6, /8, /16 on Each Output Individually
  • Efficient Jitter Cleaning From Low PLL Loop Bandwidth
  • Low Phase Noise PLL Core
  • Programmable Phase Offset (PRI_REF and SEC_REF to Outputs)
  • Wide Charge Pump Current Range From
    200 μA to 3 mA
  • Dedicated Charge Pump Supply (VCC_CP) for Wide Tuning Voltage Range VCOs
  • Presets Charge Pump to VCC_CP/2 for Fast Center-Frequency Setting of VC(X)O
  • Analog and Digital PLL Lock Indication
  • Provides VBB Bias Voltage Output for Single-Ended Input Signals (VCXO_IN)
  • Frequency Hold-Over Mode Improves Fail-Safe Operation
  • Power-up Control Forces LVPECL Outputs to 3-State at VCC < 1.5 V
  • SPI Controllable Device Setting
  • 3.3-V Power Supply
  • Packaged in 64-Pin BGA (0.8 mm Pitch – ZVA) or 48-Pin QFN (RGZ)
  • Industrial Temperature Range –40°C to 85°C

2 Applications

  • Wireless Infrastructure
  • SONET
  • Data Communication
  • Test Equipment

3 Description

The CDCM7005 is a high-performance, low phase noise and low skew clock synchronizer that synchronizes a VCXO (voltage controlled crystal oscillator) or VCO (voltage controlled oscillator) frequency to one of the two reference clocks. The programmable pre-divider M and the feedback-dividers N and P give a high flexibility to the frequency ratio of the reference clock to VC(X)O

VC(X)O_IN clock operates up to 2.2 GHz. Through the selection of external VC(X)O and loop filter components, the PLL loop bandwidth and damping factor can be adjust to meet different system requirements.

The CDCM7005 can lock to one of two reference clock inputs (PRI_REF and SEC_REF), supports frequency hold-over mode and fast-frequency-locking for fail-safe and increased system redundancy. The outputs of the CDCM7005 are user definable and can be any combination of up to five LVPECL outputs or up to 10 LVCMOS outputs. The built in synchronization latches ensure that all outputs are synchronized for low output skew.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
CDCM7005 VQFN (48) 7.00 mm × 7.00 mm
BGA (64) 8.00 mm × 8.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Typical Application Schematic

CDCM7005 Key Graphic.gif

4 Revision History

Changes from F Revision (July 2015) to G Revision

  • Removed duplicate row: PRI_SEC_CLK.Go
  • Changed text from: "STATUS_REF or" to: "STATUS_REF or PRI_SEC_CLK".Go

Changes from E Revision (February 2013) to F Revision

  • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go

Changes from D Revision (August 2009) to E Revision

  • Changed PLL_LOCK pin description, replaced cycle-slip text.Go
  • Changed the Frequency Hold-Over Mode sectionGo
  • Changed text From: Cycle-Slip To: Frequency Offset in Figure 21Go
  • Changed Note 1 of table Word 3Go
  • Changed table Word 3, Cycle Slip (Bit 6) To: Frequency OffsetGo
  • Changed table Lock-Detect Window (Word 3) - Clip slip To: Frequency offset, and Note 2Go

Changes from C Revision (December 2007) to D Revision

  • Added text to the CTRL_CLK pin - Unused or floating inputs must be tied to proper logic level. A 20kΩ or larger pull−up resistor to VCC is recommended. Go
  • Added text to the CTRL_DATA pin - Unused or floating inputs must be tied to proper logic level. A 20kΩ or larger pull−up resistor to VCC is recommended. Go
  • Added text to the CTRL_LE pin - Unused or floating inputs must be tied to proper logic level. A 20kΩ or larger pull−up resistor to VCC is recommended. Go
  • Added text to the PD pin - It is recommended to ramp up the PD with the same time as VCC and AVCC or later. The ramp up rate of the PD should not be faster than the ramp up rate of VCC and AVCC.Go
  • Changed VCC pin text From: 3.3-V supply. There is no internal connection between VCC and AVCC. It is recommended that AVCC use its own supply filter. To: 3.3-V supply. VCC and AVCC should always have the same supply voltage. It is recommended that AVCC use its own supply filter.Go
  • Added text to the SPI CONTROL INTERFACE section - Unused or floating inputs must be tied to proper logic level. A 20kΩ or larger pull−up resistor to VCC is recommended. Go
  • Added text to the SPI CONTROL INTERFACE section - It is recommended to program Word 0, Word 1, Word 2 and Word 3 right after power up and PD becomes HIGH.Go
  • Changed From: RES To: GTMEGo
  • Changed From: RES To: PFDFCGo

Changes from B Revision (October 2005) to C Revision

  • Changed N2, From: 1 To: 0Go
  • Changed N3, From: 1 To: 0Go
  • Changed N3, From: 1 To: 0Go
  • Changed N2, From: 1 To: 0Go

Changes from A Revision (June 2005) to B Revision

  • Added minor updates.Go

Changes from * Revision (June 2005) to A Revision

  • Changed data sheet from Product Preview to Production data.Go