SLUSD83C
june 2018 – may 2023
BQ25713
,
BQ25713B
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Revision History
5
Description (continued)
6
Device Comparison Table
7
Pin Configuration and Functions
8
Specifications
8.1
Absolute Maximum Ratings
8.2
ESD Ratings
8.3
Recommended Operating Conditions
8.4
Thermal Information
8.5
Electrical Characteristics
8.6
Timing Requirements
8.7
Typical Characteristics
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Power-Up from Battery Without DC Source
9.3.2
Vmin Active Protection (VAP) when Battery only Mode
9.3.3
Power-Up From DC Source
9.3.3.1
CHRG_OK Indicator
9.3.3.2
Input Voltage and Current Limit Setup
9.3.3.3
Battery Cell Configuration
9.3.3.4
Device Hi-Z State
9.3.4
USB On-The-Go (OTG)
9.3.5
Converter Operation
9.3.5.1
Inductance Detection Through IADPT Pin
9.3.5.2
Continuous Conduction Mode (CCM)
9.3.5.3
Pulse Frequency Modulation (PFM)
9.3.6
Current and Power Monitor
9.3.6.1
High-Accuracy Current Sense Amplifier (IADPT and IBAT)
9.3.6.2
High-Accuracy Power Sense Amplifier (PSYS)
9.3.7
Input Source Dynamic Power Manage
9.3.8
Two-Level Adapter Current Limit (Peak Power Mode)
9.3.9
Processor Hot Indication
9.3.9.1
PROCHOT During Low Power Mode
9.3.9.2
PROCHOT Status
9.3.10
Device Protection
9.3.10.1
Watchdog Timer
9.3.10.2
Input Overvoltage Protection (ACOV)
9.3.10.3
Input Overcurrent Protection (ACOC)
9.3.10.4
System Overvoltage Protection (SYSOVP)
9.3.10.5
Battery Overvoltage Protection (BATOVP)
9.3.10.6
Battery Short
9.3.10.7
System Short Hiccup Mode
9.3.10.8
Thermal Shutdown (TSHUT)
9.4
Device Functional Modes
9.4.1
Forward Mode
9.4.1.1
System Voltage Regulation with Narrow VDC Architecture
9.4.1.2
Battery Charging
9.4.2
USB On-The-Go
9.4.3
Pass Through Mode (PTM)
9.5
Programming
9.5.1
I2C Serial Interface
9.5.1.1
Data Validity
9.5.1.2
START and STOP Conditions
9.5.1.3
Byte Format
9.5.1.4
Acknowledge (ACK) and Not Acknowledge (NACK)
9.5.1.5
Slave Address and Data Direction Bit
9.5.1.6
Single Read and Write
9.5.1.7
Multi-Read and Multi-Write
9.5.1.8
Write 2-Byte I2C Commands
9.6
Register Map
9.6.1
Setting Charge and PROCHOT Options
9.6.1.1
ChargeOption0 Register (I2C address = 01/00h) [reset = E70Eh]
9.6.1.2
ChargeOption1 Register (I2C address = 31/30h) [reset = 0211h]
9.6.1.3
ChargeOption2 Register (I2C address = 33/32h) [reset = 02B7h]
9.6.1.4
ChargeOption3 Register (I2C address = 35/34h) [reset = 0030h]
9.6.1.5
ProchotOption0 Register (I2C address = 37/36h) [reset = 4A65h]
9.6.1.6
ProchotOption1 Register (I2C address = 39/38h) [reset = 81A0h]
9.6.1.7
ADCOption Register (I2C address = 3B/3Ah) [reset = 2000h]
9.6.2
Charge and PROCHOT Status
9.6.2.1
ChargerStatus Register (I2C address = 21/20h) [reset = 0000h]
9.6.2.2
ProchotStatus Register (I2C address = 23/22h) [reset = A800h]
9.6.3
ChargeCurrent Register (I2C address = 03/02h) [reset = 0000h]
9.6.3.1
Battery Precharge Current Clamp
9.6.4
MaxChargeVoltage Register (I2C address = 05/04h) [reset value based on CELL_BATPRESZ pin setting]
9.6.5
MinSystemVoltage Register (I2C address = 0D/0Ch) [reset value based on CELL_BATPRESZ pin setting]
9.6.5.1
System Voltage Regulation
9.6.6
Input Current and Input Voltage Registers for Dynamic Power Management
9.6.6.1
Input Current Registers
9.6.6.1.1
IIN_HOST Register With 10-mΩ Sense Resistor (I2C address = 0F/0Eh) [reset = 4100h]
9.6.6.1.2
IIN_DPM Register With 10-mΩ Sense Resistor (I2C address = 25/24h) [reset = 4100h]
9.6.6.1.3
InputVoltage Register (I2C address = 0B/0Ah) [reset = VBUS-1.28V]
9.6.7
OTGVoltage Register (I2C address = 07/06h) [reset = 0000h]
9.6.8
OTGCurrent Register (I2C address = 09/08h) [reset = 0000h]
9.6.9
ADCVBUS/PSYS Register (I2C address = 27/26h)
9.6.10
ADCIBAT Register (I2C address = 29/28h)
9.6.11
ADCIINCMPIN Register (I2C address = 2B/2Ah)
9.6.12
ADCVSYSVBAT Register (I2C address = 2D/2Ch)
9.6.13
ID Registers
9.6.13.1
ManufactureID Register (I2C address = 2Eh) [reset = 0040h]
9.6.13.2
Device ID (DeviceAddress) Register (I2C address = 2Fh) [reset = 0h]
10
Application and Implementation
10.1
Application Information
10.2
Typical Application
10.2.1
Design Requirements
10.2.2
Detailed Design Procedure
10.2.2.1
ACP-ACN Input Filter
10.2.2.2
Inductor Selection
10.2.2.3
Input Capacitor
10.2.2.4
Output Capacitor
10.2.2.5
Power MOSFETs Selection
10.2.3
Application Curves
11
Power Supply Recommendations
12
Layout
12.1
Layout Guidelines
12.2
Layout Example
12.2.1
Layout Example Reference Top View
12.2.2
Inner Layer Layout and Routing Example
13
Device and Documentation Support
13.1
Device Support
13.1.1
Third-Party Products Disclaimer
13.2
Documentation Support
13.2.1
Related Documentation
13.3
Receiving Notification of Documentation Updates
13.4
Support Resources
13.5
Trademarks
13.6
Electrostatic Discharge Caution
13.7
Glossary
14
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RSN|32
MPQF194B
Thermal pad, mechanical data (Package|Pins)
RSN|32
QFND189E
Orderable Information
slusd83c_oa
slusd83c_pm
Data Sheet
BQ25713, BQ25713B I
2
C Narrow VDC Buck-Boost Battery Charge Controller With System Power Monitor and Processor Hot Monitor